RTL Verification Engineer- 6 month contract San Francisco, CA

Develop and maintain RTL simulation and regression tests for FPGAs.

Develop BFM’s and simulation test benches, and maintain automatic regression tests.

Responsible for implementing FPGA regression tests, reporting and tracking bugs, and FPGA release tracking.

Help lead the simulation/verification infrastructure.

Support the development of a hardware-based regression/continuous integration setup.

Requirements

5+ years of professional experience.

Familiarity with SystemVerilog, SystemVerilog assertions, and SystemVerilog constrained randomization.

Experience with Python or similar scripting languages such as tcl, bash, csh, or Perl.

Extensive experience in either FPGA or ASIC verification (or both)

Experience with C/C++, SystemVerilog DPI, and related software build tools (GNU gcc/make)

Bonus

Experience in UVM (or OVM/VMM/AVM/Specman)

Experience with existing regression tools, to automatically track bugs (e.g., coverage aggregation tools or similar)

Pay Rate-65-80/hr. DOE

Please send resume to kjohnson@nelsoninteractive.net